The well known and ongoing movement in the semiconductor industry toward further miniaturization of semiconductor devices has required regular increases in the density of devices placed on IC substrates. This, in turn, has necessitated reductions in the dimensions of the devices themselves and of their components. For example, the dimensions of gates, and the channel separation of source and drain elements, have become progressively smaller.
The aforementioned trend presents issues for the performance characteristics, reliability, and durability of semiconductor devices. In particular, as semiconductor devices continue to shrink in size, problems with short channel effects, punch-through, and current leakage become more pronounced. These problems have significant adverse impacts on the performance of semiconductor devices, and greatly complicate the manufacturing processes used to fabricate these devices.
In particular, as channel lengths are reduced, the source and drain depletion regions are disposed in closer proximity to each other. In such short channel devices, the drain begins to influence the channel and reduces the influence of the gate. This phenomenon is known as the short channel effect. The impact of the short channel effect on device performance is often manifested as a reduction in the device threshold voltage or as an increase in the sub-threshold current.
One method for reducing or eliminating short channel effects is to reduce the thickness of the channel region between the source and drain. This may be accomplished, for example, through the use of FDSOI devices or ultra-thin body devices. Even better short channel control is possible by providing gates on either side of this thin channel region, since two gates control the thin silicon channel region much more effectively than one and reduce the influence of the drain on the channel.
One of the outcomes of the continuing efforts to resolve the short channel effect and the other problems as noted above has been the development of FinFETs. FinFETs are field effect transistors (FETs) that are equipped with a gate electrode controlling a thin vertical fin-shaped channel region. One example of such a device is depicted in FIG. 1. The device depicted therein is fabricated on a dielectric layer 2 and includes a silicon drain island 4 and a source island 6 that are connected by a silicon fin or channel 8. The source, drain, and channel are covered by a dielectric layer or hard mask 9 during a stage of the process, and a gate 11 extends across both sides of the channel fin 8 and is isolated from the gate 11 by a gate oxide (not shown). Thus, inversion layers are formed on both sides of the channel. Such a structure has the advantage of providing double gates to effectively suppress the short channel effect and to enhance drive current. Also, since the channels are parallel planes, parasitic corner effects are overcome. Moreover, since the fin is very thin, doping of the fin may not be required in order to suppress the short channel effect.
While FinFET devices such as that depicted in FIG. 1 have many advantages, there is still a need in the art for further improvements in these devices. For example, in some conventional FinFET designs, when more current is needed from a FinFET, fins are added in parallel with the gate extending over each of the fins. Hence, in order to get increased current for a given area, the pitch of the fins (that is, the distance equal to the width of the fins and the space between the fins) has to be minimized. Unfortunately, it has proven difficult to achieve further reductions in the pitch of FINFET devices beyond the values already achieved, due to fundamental limitations in existing lithography techniques. In particular, the line edge roughness (LER, which is a measure of the variation in line width along the length of a line), parallelism of the two fin sidewalls, and critical dimension (CD) variation attendant to these processes present problems for good manufacturability.
There is thus a need in the art for devices and methodologies which overcome this problem. This and other needs may be met by the devices and methodologies described herein.